The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method of forming implanted plates for high aspect ratio trenches for semiconductor devices using staged sacrificial layer removal.
Deep trench capacitors are used in a variety of semiconductor chips for high area capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from about 4 fF (femto-Farad) to about 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio frequency (RF) circuit.
Deep trench capacitors are formed in a semiconductor substrate, which can be a semiconductor-on-insulator (SOI) substrate or a bulk substrate. Other semiconductor devices such as field effect transistors (FETs) can be formed on the same semiconductor substrate, thereby enabling embedding of deep trench capacitors into a semiconductor chip. Such embedded deep trench capacitors enable various functionalities including, for example, embedded dynamic access memory (eDRAM) and other embedded electronic components requiring a capacitor.
As the size of an opening of a deep trench decreases with integrated circuit device scaling, the aspect ratio of the deep trench increases. Thus, formation of a buried plate by angled ion implantation into sidewalls of a deep trench becomes more difficult with the increase in the aspect ratio of the deep trench. There are two factors that render the formation of a buried plate by direct angled ion implantation into sidewalls of the deep trench difficult. First, a high aspect ratio of a deep trench limits the amount of implanted ions that can reach a lower portion of the deep trench, as even a small angular variation from normal incidence in the direction of the implanted ions tends to send the ions to the upper portion of the deep trench when the aspect ratio is high. Second, a spacer layer is typically used upon formation of a deep trench in order to absorb implanted ions and protect the top semiconductor layer in an SOI substrate or a top portion of a bulk substrate during ion implantation. However, such a spacer layer reduces the dimension of the opening in the upper portion of the deep trench, thus limiting the ion implantation angle even further.
On the other hand, there also exist methods of forming a trench plate without ion implantation such as, for example, gas phase doping, solid source doping, and depositing a metal plate. Still another approach involves utilizing an already doped handle wafer to serve as a pre-doped plate for the deep trenches, and growing epitaxial layer on the handle wafer, sandwiching a buried insulator layer. Unfortunately, such alternate methods tend to employ complex processing schemes and are also costly to implement.